1. Field of the Invention
The present invention relates to a circuit for generating a M-sequence (Maximum-length linear shift register sequence) pseudo-random pattern which are multiplexed in m fold. This pattern will be herein called "MRP".
2. Prior Art
The conventional MRP generator will be briefly explained in reference to FIG. 4.
In FIG. 4, the MRP generator includes a n-step shift register 1 and an exclusive logical sum gate (hereinafter called "EXOR gate") 2. 3 is an output and 10 is clock signal.
The MRP generator shown in FIG. 4 is a feedback circuit in which the n-step shift register 1 has a feedback loop by way of the EXOR gate 2. In order to generate a MRP with a high speed, the n-step shift register is actuated by a fast clock signal 10.
The highest operating speed of the MRP generator in FIG. 4 is determined by the performances of the respective elements comprising the MRP generator and thus it is not possible to attain a higher operating speed.
Accordingly, a principal object of the present invention is to provide a MRP generator having a higher operating speed than the conventional MRP generator.